Multi-Die Systems Set the Stage for Innovation
In many, many ways. 2023 was an inflection point for the semiconductor industry. Synopsys conducted surveys of keystone companies, and nearly 40% of companies surveyed indicated that they are now exploring adopting multi-die systems. That's a significant change, an increase from past years. Several years ago, Aart de Geus, the founder and chairman of Synopsys talked about the era of systems, and many of you may have heard him speak. So this denotes the coming together of systemic complexity and the ambition of Moore's Law.
Today, we are in the year of systems and writing that the core has been as an enabler. Our multi-die systems. Last year, the MIT Technology Review published a report in partnership with Synopsys. By the way, there is a wealth of information in this report. I encourage you to download this report from the synopsys.com website when you get a chance.
And in this report, Sassine Ghazi, the CEO of Synopsys, had a quote. And in this quote, there were two key messages. One is innovation across the technology stack and the second is collaboration.
Both of these are essential and important for the multi-die industry. And I've talked about that in more detail. So if you look at the progression of designs and design complexity, starting with designing with schematics, and some of you here may remember those days, maybe you do not want to admit, admit it. The first inflection point was the introduction of HDL, hardware description languages.
This allowed designing larger chips faster with better performance, BPA, better performance, power and area. It opened up the pathways of synthesis, test verification, automatic placement route. You are all familiar with that. I led the synthesis franchise's Synopsys for over 12 years, and during that time we introduced this concept of design where IDs. So these are parametrized parenthetical units like multipliers and alias. For example, in synthesis you can pick the architecture.
You can pick a half header or full letter to carry locator. You can pick a boost multiplier. And in many ways this was a window into the possibilities of ID. Which leads us to the next inflection point, which is designing with IDs which further enabled addition of large number of functionality of a single chip.
And accomplishing this in reasonable time to results with superior quality of results and in a reliable and predictable manner. A logical progression. The next step in this logical progression is the multi-die system. And there are many drivers with this.
So and some of the earlier speakers alluded to this, that the multivariate ecosystem enables even small companies with small pocketbooks to develop complex systems where they can focus on their own competitive advantage. The differentiated value. I'm not sure if folks at the back can read the quote at the bottom. This is a quote from Roger Duty of Intel, where he says there's a 1,000x more compute demand for AI over 2025, and you hold a thousand x number in previous presentations as well. So that's, of course, a key driver. But there are other drivers.
And again, the previous speakers I've spoken to them. So just to summarize what they mentioned. Disaggregation modularity provides additional flexibility and configurability.
It allows the end user or the architect to trade off cost and performance metrics. You can mix and match, mix and match dies. You can choose to have a die, you know, you can the node and save costs during the pandemic time. There was this concern about supply chain. And during the time, there was a lot of conversation about heterogeneous integration, about multiple-dies and chiplets, because that enables architects to infer when they were not getting enough seats at the table and foundry houses when there were hitting capacity limits.
It enables architects to pivot and design some of their dies with the more advanced nodes, and also using onshore fabs. There are, of course, advantages of quality of results, better travel and electrical performance, predictability. Lower the risk, better time to results, better yield. In 2023, Gartner released forecast. And they estimated that the 3D IC market is expected to exceed $55 billion, with the CAGR over 30% in the next five years.
And there are other forecasts as well, which have extremely bullish trends with high double digit category in for the chip industry. If you look at the data, the data seems to defend these forecasts. And so there's a lot of momentum behind it. The table on the left shows the number of design starts by year. And the purple portion is the number of designs starts with chiplets or multi-die design starts.
It's projected that in 3 to 4 years by 2027, over half of the design starts will have chiplets. So that's a significant number. And it's very exciting. The data on the right from Synopsys and looked at design starts in 2023, and nearly 50% of the design starts .... This is not a surprise.
There's also healthy participation from other segments. About a portion of the design starts is from networking and automotive combined. And then there's also participation in bid servers, consumers, storage, etc.. And those who attended the presentation from you earlier in the morning, there was an interesting data that we shared which I'm presenting here again, and this data shows the number of the volume of units, the number of units produced by year and divided into different segments. It's not a surprise that high performance computing servers, AI as well as PCs are beachheads for multi-die design and chiplets usage. The ASPs in these sectors are 1 to 3 orders of magnitude higher than ASPs, say in the consumer SoC space.
However, as the demand for adding more functions onto a chip keeps expanding in the consumer space, it's inevitable that there will be a strong market to chip place in the consumer responses. And that's exciting because if you look at the volumes in the consumer systems, it's orders of magnitude more than the volume of units produced in the other sectors. So that promises very significant time for chiplets. Now, all of this is made possible thanks to investments and advancements in many key areas.
And I'll touch upon a few of them, starting with a comprehensive solution for heterogeneous integration across the full technology stack. And I'm talking about from architecture all the way to implementation, manufacturing, test and the architecture level, there are many choices to be made. Disaggregation choices, packaging choices, floor planning.
And when you talk about 3D, how do you stack the die? And these choices have a profound impact on the metrics we care about. Thermal performance, electrical performance, cost, reliability, yield. And so these choices cannot be made in isolation. And in the previous keynote so we talked about co-optimization.
And that's an important theme for multi-die systems and large complex systems. The chip design and package design cannot be thought of in isolation. So there's is there is this notion of co-design and co-optimization that becomes important. And to facilitate that, there is there is a need for systemic analysis, multi physics. We're talking about not just looking at timing but looking at thermal power and EMR, all at the same time. And then there are the dimensions of mechanical reliability and warppage.
There is talk about ESG being an important factor as well. So so it's important to have these these analysis capability, system-level analysis capabilities available throughout the technology stack. Verification is a big problem. System-level verification where the goal is to have very high coverage without a massive vacuum explosion, which can be prohibitive in terms of time and results, or to verify in a timely manner use of silicon proven IP and IP chiplets, and then last but not the least, lifecycle management, monitor, test and repair. The ability to debug problems in the large complex system quickly. And even better, if we are able to detect problems before they happen and fix them or repair them.
Perhaps in the field, that's a tremendous value because the cost of failure is very high. So these capabilities exist today, and Synopsys is continuing to invest in the in this space. Another key enabler is advanced packaging.
And the previous speakers talked about this. Organic substrates and wafer level packaging, a relatively low cost and have had decent adoption across different sectors. Silicon interposers and how the bonding of a higher interconnect density. Now high interconnect density is important, and it enables more applications to benefit from the multi-die systems. There is continuous advancements and investments in the packaging industry in packaging technology.
In parallel, there is a lot of investment by foundries to grow the size of the device that is manufactured. Recently, TSMC announced a plan to grow a Super Carrier interposer size using leveraging the new CoWoS-L technology with the efficiency of manufacturing of fabricating a die six times the original size limit, six times. So that's very exciting and and exciting and bodes well for the multi-die industry.
So fanout wafer package has seen a lot of adoption, particularly in the mobile and wireless space, wireless basebands, for example, and is making its way to the automotive and medical sectors. Now, the linear interconnect density of the fanout wafer level package makes it possible for disaggregation. It's lot interconnect density is a lot higher than organic substrates, and the relative cost of the packaging compared to, say, hybrid bonding makes it attractive as well. It has good electrical performance, thermal properties, as well as the package size itself is almost the size of the die size, which is of course, an important property that makes it attractive. On the right hand side is an example shared by DECA at the 2022 SNUG event, where they took a monolithic SoC and broke it up, disaggregated it into 12 dies, and connected them with five redistribution layers as shown in the bottom here. And this connection was possible because of fanout wafer level packaging.
The bond, which was less than 20 microns, line and space was less than two microns, and that provided the wire spending millimeter of the interconnect density needed to make this happen. And as a result, we have a multi-die system with all the benefits that come with it. A lower cost system with higher yield than a monolithic SoC. As a design complexity grows, the opportunity for AI to improve productivity and TTR, time to result, significantly is is is huge. And so previous topic speakers have spoken about this opportunity as well. And I think there are several sessions that address this as well.
So the opportunity is in many different segments. There is a collaborative segment where it can help with answering questions, perhaps even product level questions. How do I do this? Analyzing your workflows. Am I doing the right thing? Is there a better way of doing things to taking it to the next level of sophistication, of creating these workflows.
Flows, for example, for design implementation, perhaps even RTL generation, assertion text generation, and then for the sophistication of exploring the design space, which is pretty massive for these large, complex designs. And so doing this design space optimization, PPA optimization, quality result optimization, and then certain segments like verification, where the system level verification to achieve very high levels of coverage can be prohibitive in terms of runtime. So there is an opportunity with for AI to help maximize the coverage while minimizing, for example, the pattern count.
And there are several such examples and some of these solutions exist today. And this is another space where Synopsys continues to invest heavily. The importance of ecosystem cannot be underestimated.
Synopsys is deeply engaged with many stakeholders and keystone companies with the objective of developing interoperability standards, developing solutions and methodologies, investing in research and development, and partnering with third party solutions, best-in-class solutions to ensure that we have the best solution, the most efficient solution available for our end customers’ end-to-end core technology stack. A shining example of the ecosystem is the UCIe or Universal Interconnect Express that you all are familiar with. A group of member companies got together and made this happen. The UCIe is a foundational standard, is a seminal standard which enables interconnecting dies These dies could be from different vendors, they could be from different technology nodes. It has good performance latency protocols. It has support for the full protocol stack.
It's comprehensive and future proof, but more work needs to be done. Intel Foundry, TSMC, and Synopsys joined together, collaborated and developed the first test chip for UCIe, code named Pike Creek. This quote below from Pat Gelsinger, Intel CEO. He gave this quote at the Intel Innovation last year. He said the first test chips for UCIe and the beginning of the chiplets era.
So whenever I see this code, I feel the tingling. It reminds me of this famous quote from Neil Armstrong. The first step on the moon. One giant leap for mankind. It feels that way, doesn't it? I'm pumped up. I'm charged up.
Last year at the TSMC Open Innovation Platform, where the TSMC and Synopsys announced the results of a collaboration where two dies communicated with each other using high speed UCIe-based interface, IPs and GPIOs as well, general-purpose IO interfaces IPs as well, but a key objective is to showcase the power and importance of MTR IPs, or monitor, test and repair IPs. Like I explained earlier, for a large system, MTR is monitor, test and repair becomes very important and this project leverages TSMC’s CoWoS, or chip on wafer on substrate interposer technology. Another example is developing is this example where a multi-die system was developed and it exercised the full technology stack. This was a collaboration with Alchip. Alchip is one of the large e-cig vendors. They also provider of advanced technology of packaging technology solutions.
And in this project or exercise production proven 2.5D packaging technology was used from Alchip, along with the full PDA stack and silicon prototype being from Synopsys. And this this project exercise a whole technology stack from architecture. So floor exploration to multi physics thermal power analysis to using IP with 3D fabric technology rules analyzing the package choices I/O pumping, hybrid bonding analysis, guidelines for CPU or signal integrity, power integrity and so on.
The objective was to increase the RAM for easy adoption for our customers to to ease their shift to a chiplet’s multi-die. So where are we today with multi-die systems? The usage today is driven by a large measure by data centers. All of you are aware of that. But there is a shift towards chiplets in other segments as well. Other speakers talked about automotive.
The 2.5D chiplet based approaches trending in the automotive sector, and in the mobile sector, where form factor is important, 3D chiplet based designs are trending. There are other sectors where cost is important. For example, we see the user organic interposers UCIe was a seminal standard.
More work needs to be done. For example, expanding this protocol, this standard to stacking. Standard languages and standardization for capturing rules for testing test methodologies are important, among others, that so standardization remains an important area that we need some progress on. Productivity, I talked about that there are lots of opportunities, including full automation in the 3D space, design space optimization, and in the 3D model, the multi-die system itself, a generalized solution for logic-on-logic stacking, as well as adoption of from end-to-end automation. Now, if you see if you take a note, or take a pause to see what we have today, there is a significant demand for large, complex designs. You hear about silicon everywhere, silicon to software.
Customer is building their own silicon for different solution. All of this is driving the growth of the semiconductor industry. So the demand is available. and if you look at the benefits of multi-die systems, they cater to this demand very well. Low cost, high yield, time to results, mix and match configurability, flexibility of the dies, modularity, etc. If you look at the enablers terms of end-to-end technology, stack in advanced packaging, ecosystem, AI, etc.
that is available today, of course, a lot more work, a lot of investment is needed. It it seems that now is a time where we will see a significant growth in the usage of the chiplets and multi-dies. And let me leave you with this note. That the more designs that use chiplets this in turn will have a positive feedback cycle which will induce more investment, more research, more advancements in this whole ecosystem of chiplets and multi-dies, which in turn will fuel more usage. And it seems to me that we are at this point today, this inflection point today. So the time is now.
Let's work together to make it happen.
2024-02-25 23:56
